As the on-chip signal switching speeds exceed multi-gigahertz (GHz) and chip densities cross several millions of transistors, parasitic capacitive coupling between adjacent metal wires and the resistive-capacitance (RC) delay due to metal resistance are becoming significant. Crosstalk induced by capacitive coupling between metal wires may degrade signal quality, achievable data bandwidths, power efficiency and interconnect reliability.
Although these problems can be alleviated by increasing wire-to-wire spacing and decreasing parallel-run length between adjacent links, both of these solutions increase the routing complexity and the area necessary to route metal wires. Signal shielding using grounded metal wires may provide isolation from crosstalk noise. However, signal shielding can increase the metal routing area by 50%. Regular twisting of interconnect suppresses crosstalk in differential links. Yet, twisting requires vias and additional metal layers. The use of vias can increase wire resistance while additional metal layers complicates routing.
In addition, the aggregate bandwidth demands of chip-to-chip data communications are growing faster than the number of available I/O pins on chips, pushing the data rates of individual links even higher. Each individual link transmitting in the Gb/s range is typically a differential link which requires two input/output (I/O) pins per chip. Single-ended signaling, which requires only one wire (and hence one pin per chip) per link has also been unsuccessful in the Gb/s range owing to the problems caused by switching noise on the supply rails.
Accordingly, there is a need to develop an improved technique for routing on-chip wires that does not increase routing complexity, chip area, or increase wire resistance, and decreases signal degradation while permitting closer routing of wires over longer distances. There is also a need to develop improved techniques for minimizing the number of I/O pins used to transmit data between integrated chips and other circuitry.